Chips are embedded in every aspect of our modern society. They can deliver high-performance, high-reliability, secure, energy-efficient, and sustainable solutions to important societal applications, including transportation, finance, education, health, defense, and entertainment. Thus, research in this area has far-reaching implications.
Professor Ahmed Louri, an IEEE Fellow, David and Marilyn Karlgaard Endowed Chair Professor, recipient of the IEEE Computer Society Edward J. McCluskey Technical Achievement Award, and the Distinguished Scholar of the Office of OVPR Award, and his team regularly investigate these novel parallel computer architectures and technologies. His current research projects include versatile and scalable accelerator architectures and chips for artificial intelligence (AI) applications.
In Spring 2023, he was awarded three new National Science Foundation (NSF) awards that total $3.8 million to continue researching and designing next-generation computing architectures. Learn more about each study below.
Sustainable Computing Systems
With the explosion of computing devices and systems in everyday consumer electronics and the advent of AI, the energy required to power information and computing technologies is reaching close to 8% of worldwide carbon emissions. NSF’s Directorate for Computer and Information Science and Engineering (CISE) created the Design for Environmental Sustainability in Computing (DESC) program to support projects that address the substantial environmental impacts that computing has through its entire lifecycle.
Professor Louri was the first to receive a $2 million, four-year grant from the CISE directorate for the project “Multi-Function Cross-layer Electro-Optic Fabrics for Reliable and Sustainable Computing Systems.” He has been designing computing architectures and hardware chips for several decades. However, the environmental impact of today’s computing and networking systems has prompted Professor Louri to recently orient his research toward designing high-performance, smaller, scalable, reliable, secure, and powerful architectures that are also sustainable with a better carbon footprint all the way from conception to deployment. In this project, Professor Louri and his team will work to improve the sustainability of computing systems via the three universally accepted tenets of reuse, reduce, and recycle.
The team will start by first exploiting existing electronic and emerging silicon photonics to design computation and communication engines, thereby reusing the same hardware architectures. Then, as reliability is critical, they plan to recycle the hardware to extend its lifetime through self-healing techniques for the dual-purpose electro-optic fabric and architectures. Lastly, they plan to reduce the operational energy using dynamic voltage and frequency scaling (DVFA) and cross-layer optimization techniques. The combined effects of these three research thrusts will significantly reduce the impact of embodied and operational energy of future hardware and consequently provide a much more sustainable computing and networking environment.
“I am very excited about this research direction as the proposed research bridges a very important gap between electronic computing systems, photonic technology, computer architecture, machine learning applications, manufacturing, and sustainability requirements,” Professor Louri stated. “Due to this cross-cutting nature, it will have far-reaching impacts and foster new research directions in several areas, from computer architecture and silicon photonics to algorithms and applications, with the potential to significantly transform the design of next-generation sustainable computing systems.”
Energy-efficient chiplet-based architectures
Another barrier to scalable computing performance includes power dissipation. Chiplet-based architectures are being heralded as a scalable solution that effectively integrates multiple dies, accelerators, and heterogeneous multicores. At the same time, Network-on-Chips (NoCs) have also been proposed for inter-chiplet communication, as larger communication distances and multiple hops hinder the system’s scalability and affect performance.
To dramatically reduce power consumption and provide scalability, disruptive technology such as silicon photonics has been proposed as it can improve the performance-per-Watt when compared to electrical implementation. In the $1.2 million research project, “EPIC: Exploiting Photonic Interconnects for Resilient Data Communication and Acceleration in Energy-efficient Chiplet-based Architectures,” Professor Louri plans on designing a novel, dual-purpose photonic fabric that will not only enable power-efficient and scalable on-chip communications for heterogeneous multicores but will also function as a cost-efficient and high-performance neural network accelerator for diverse applications over the next three years.
“The crux of the idea is to (1) provide high-bandwidth and power-efficient data transfer between cores and accelerators during high network load, and (2) off-lead key accelerator functions to the same network during low network load to maximize resource utilization and speed up computation, hence the dual-purpose nature of the fabric,” Professor Louri stated.
It is expected that the combined efforts of meticulously orchestrating data communication both on- and off-chip, sharing hardware resources between communication and computation, and implementing optical neural computations will provide an extremely power-efficient and scalable platform for next-generation heterogeneous chiplet-based architectures.
Resilient multicore systems
The proliferation of multiple cores on the chip has signaled the advent of communication-centric rather than computation-centric systems. Consequently, designing low latency, power-efficient, and reliable on-chip interconnects is proving to be one of the most critical challenges for future multicore chips. Industry and academic researchers have adopted NoC as the communication fabric to address this challenge.
However, as technology keeps scaling down, unpredictable device behavior will undeniably increase and result in a significant increase in both permanent and transient faults and hardware failure. Professor Louri says current solutions are inadequate to deal with the increased number of hardware failures. In the $600,000, three-year project, “Cross-layer Learning-based Energy-efficient and Resilient NoC Design for Multicore Systems,” he proposes a machine-learning-enabled, cross-layer approach for designing these systems to be resilient and energy-efficient.
Professor Louri’s overarching goal is to enable cooperation and dynamic adaptation across all system abstraction layers to obtain globally optimal solutions for system-level reliability, performance, power, and cost. To achieve this goal, he proposes four interrelated research tasks that span various areas from interconnect microarchitecture design to machine learning algorithms and applications to proof-of-concept implementation.
Connecting the studies
The research projects, while distinct, are interrelated and contribute to Professor Louri’s vision of designing next-generation computing architectures that will be smaller, faster and more powerful, reliable, secure, and sustainable with application to many societal needs. These projects will not only advance the science of designing next-generation computing systems but will also play a major role in education by integrating discovery with teaching and training.
“I am committed and will continue to expand on outreach activities and broaden participation in computing by making the necessary efforts to attract and train underrepresented and minority students in this exciting field,” said Professor Louri.