Lab Work

• Lab 1: Introduction to Verilog:
  • Setting up your Unix Environment for Synopsys, & Cadence Tools
  • In Class Work & Lab Assignment 1
  • Notes on Verilog
  
  
• Lab 2: Introduction to Synopsys - Synthesis:
  • Synthesizing Lab1 full adder
  • Synopsys Design Compiler Constraints manual
  
  
• Lab 3: Verilog Test Bench Design:
  • Verilog Test Bench Design discussion and assignment
  • Structured Test Bench example: DFF Test bench
  • DFF Test Bench waveform
  
  
• Lab 4: Introduction to Synopsys - Tetramax ATPG:
  • Using Synopsys TetraMax to Generate ATPG Patterns for Full Adder
  • Synopsys Design Compiler DFT User Guide
  • Synopsys TetraMax ATPG User Guide
  
  
• Lab 5: Introduction to Synopsys - DFT Compiler & Tetramax Scan Chain ATPG:
  • DFT Scan Chain insertation into Ripple Carry adder
  
  
• Lab 6: Introduction to Synopsys BSD Compiler:
  • Boundry Scan Core insertion with BSD Compiler
  • BSD Compiler Manual
  
  
• Lab 7: Introduction to Cadence Encounter - Place & Route Tool:
  • SPRING 2011 Students RUN ME BEFORE YOU START LAB 7
  • Place and Routing the Ripple Carry Adder w/Scan Cells
  • Cadence Silicon Encounter Reference Manual
  • Cadence Silicon Encounter User's Guide
  • Cadence Silicon Encounter Nanorouter Guide
  
  
• Lab 8: Introduction to Cadence Chip Assembly Router - Automatic Chip Routing and Assembly Tool:
  • CCAR - Automatic Core to Core & Core to Pad routing
  • Cadence Chip Assembly Router documentation is available under the Cadence Help in our Unix Environment
  Guide
  
  
• Lab 9: CPU Project Lab 1 - Synthesis of ALU, Regfile, Controller
  • Project setup & Synthesis Instructions
  
  
• Lab 10: CPU Project Lab 2 - Synthesis of datapath and pc controller
  • Synthesis of datapath and pc controller
  
  
• Lab 11: CPU Project Lab 3 - DFT insertion
  • RUN THIS PRIOR TO LAB11
  • Synthesis of CPU & DFT insertion
  
  
• Lab 12: CPU Project Lab 4 - P&R of CPU
  • RUN THIS PRIOR TO LAB11
  • TB, P&R, CCAR of CPU
  
  

Useful Cadence/Synopsys Tutorials

• Tutorial 1: Procedural Style Verilog - Creating a comparitor
• Tutorial 2a: VerilogA - Creating a resistor (Lecture)
• Tutorial 2b: VerilogA - Creating a resistor (Lab)
• Tutorial 3: Using HiLevel machine to test chips Tompkins Rm 309
• Tutorial 4: ScanFF Cell Design Guide
• Tutorial 5: Encounter Library Characterizer notes

Project Files

• CPU Project Documentation
• TinyMIPS simulation guide
• TinyMIPS correct simulation waveform


• CPU Test Files

Old Exams

• Midterms
• Midterm S04 - with solutions
• Midterm S08 - no solutions available

Links

• Chip Testing: Using the Agilent Logic Analyzer to test CMOS chips
  • Logic Analyzer Tutorial + Lab
  
  
• Interesting Verilog Projects and Links
• VerilogA Language Reference
• VLSI Design at University of Michigan
• VLSI Design at Stanford
• VLSI Design at NCSU