VLSI technology has become a major driving force in the development of all types of electronic systems. This course will is a continuation of ECE 126. ASIC design methodology, use of ASIC design CAD tools, and testing methodology will be introduced. An introduction to logic synthesis, styles of synthesis, and the purpose and nature of power/area/speed constraintswill be given. As an introduction to VLSI testing, fault models, design for testability techniques, scan path, JTAG, and Built-in-self-test methods will be incorporated. The course is designed to teach students about Higher Methodology for VLSI design and include Design For Test (DFT) techniques. Student will use VLSI lab to test their designed Chip and will use CADENCE CAD tool to design and include DFT methods.Students must test in the laboratory previously-designed ECE 126 chips. May be taken for graduate credit.