|
Project Information
Each student must complete a VLSI project design that will count for 40% of his or her grade
for the entire course. The project is to be completed by a team of two students, who will be
credited with the grade. The project deliverables are as follows:
| 1st report, Project Proposal (title and topic abstract) |
| 2nd report, Project Final Report |
Project Topic
The first step in producing a good project is careful planning. The reason there is a good correlation between a good project proposal and successful project is that a good project proposal shows evidence of careful planning and enthusiasm. The most important part of selecting a project is:
- Select an application that you know well.
- First, simulate your idea using a HDL (if available) or logic simulator and make sure your idea actually works at the gate level.
- DO NOT choose an oversized project ... you must COMPLETE the project within the time frame you have.
- The project should be suitable for partition into a simpler project if you are running out of time. It is possible to make it more ambitious if the solution turns out to be too simple.
- The project should be useful to you, maybe to other projects you are working on.
For your project, you will be doing two complete designs either comparing two different
implementations of the same microarchitecture (e.g., a 50 bit static pipeline latch
versus a 50 bit dynamic pipeline latch) or two different microarchitectures implementing
the same function (e.g., a 16 bit carry select adder versus a 16 bit carry bypass adder; a
2-read port, 1-write port register file versus a 4-read port, 2-write port register file; a
fast 32 bit adder with and without MMX support; a 16 bit multiplier using 4-2 counters with
and without pipelining). Projects should contain two to four different "logic blocks" which
are to be designed, simulated, and compared separately (for the Prototype Report) and then
merged and simulated and compared as two complete designs for the Final Report. You may select
one of the topics listed below, or you may come up with one of your own; however, the
instructor must approve the project topic. This approval will be part of the grading process
for the Project Proposal report.
Some project suggestions:
- 16bit fast adder/subtractor (carry select, carry bypass, parallel prefix, ?)
- 16bit shifter (barrel, logarithmic)
- 8bit by 8bit array multiplier (pezaris, leap-frog, ?)
- 8bit by 8bit partial product array reduction tree (with/without multiplier recoding; with/without pipelining)
- 8bit divider (restoring, non-restoring, array, SRT, ?)
- A study of area-speed-power tradeoffs in flip-flop designs (with/without scan support)
- Four 8bit input by four-8bit output crossbar interconnection unit
- A study of area-speed-power tradeoffs in two source, two sink 16bit bus designs (odd/even bus invert, low swing, ?)
- An 8word, 16bit multiport register file (2-read ports, 1-write port vs 4-read port, 2-write port vs etc.)
- ¼ Kbit (16rows by 16bit static) RAM (with/without read buffer; with/without partitioning)
- 8word, 20bit (3bit tag, 16bit data) CAM
- SECDED (single error correction, double error detection) logic for a 16bit word memory output
- An 8 entry by 16bit instruction issue queue (compacting vs. non-compacting)
- Compression/decompression blocks (e.g., Huffman codes)
- Encrypter/decrypter
- LDPC (low-density parity check code) decoder
- Asynchronous interface logic (handshaking logic and data queue)
- FPGA logic blocks and interconnects
- Reorder buffer
Project Report Format
All reports must include a header section stating report type (proposal,
specification, prototype, or final), title, team members, and date. The
project title should clearly identify the project, so be careful to select
a meaningful title. Each report should be a technical document as would be
intended for your employer or your customer. Always include a written description
(caption) for any figure, diagram, Cadence layout or schematic, simulation (SpectreS)
input files and output waveforms/text, etc. Figures and diagrams should be included
where appropriate (check out xfig, xv, etc.). List any other references used, and
refer to them in the text. Since all of the reports are to be submitted by installing
them in your project web page, you must create your reports so that they can be converted
into html or pdf files (e.g., with MS Word, PowerPoint, Framemaker, etc.). Only the Project
Proposal must also be turned in as a hardcopy format in class (please, only one copy per team).
No late reports will be accepted. (Temporary system problems near deadlines are not valid excuses.)
Project Proposal
This report accounts for 5% of the project grade.
The Proposal must include a header section, a one paragraph description (what it does),
whether you plan to implement two different implementations of the same architecture (and
what type of implementations are planned if you know at this point) or two different architectures
of the same function (and what two architectures are planned), an estimate of the total number of
inputs and outputs required, an estimate of the number of blocks required for each design, an
initial “floorplan” for each design (a block diagram of your project showing the blocks and their
interconnections to each other and to the I/O pins). When selecting a project, you must have
clear idea as to what you will be designing. Proposal must be no more than three pages. Specify
clearly the role of each team member in the project. Give the URL for your project’s homepage and
install the Project Proposal there.
Project Specification
This report accounts for 25% of the project grade.
The specification involves doing a complete logic design (down to the gate level) of each
block for each of your designs, so that each block is ready to implement using Cadence. You
can use any software like VHDL, Verilog, Logic Works, etc to validate your design. An error
caught at design level is lot easier to correct.
The report should include:
- Header section
- Project specification: Give a one paragraph description of the function the project performs, whether you are doing two implementation or two architectural alternatives and what those alternative are, revised floorplans with block interconnections and I/Os labeled (don’t forget power, ground, and clock), and clocking plans.
- Block specification: Give a description of each of the blocks in each of your designs. For blocks of pure combinational logic, you can give Boolean equations, truth tables, or higher-level mathematical descriptions (e.g., for a subtraction, you can say A = B-C). For state machines, a state diagram is a good description. Give transistor-level circuit diagrams only for non-standard components.
- Verification: Where possible you must simulate your designs (e.g., from VHDL or Verilog descriptions or using a schematic capture/simulation tool like Cadence/Analog Artist). Turn in your simulation input and output. Annotate the output to demonstrate that each block functions correctly and that the entire design functions correctly. Please note: if the waveforms are not self-explanatory, please annotate them with useful comments.
Note: The specification and all the reports subsequent to this one should be on the web page (the URL was supposed to have been mentioned with the title). No hardcopy is required. And please make sure that your page is accessible from the course web page (www.seas.gwu.edu/~vlsi/projects.html).
Project Prototype Report
This report accounts for 35% of the project grade.
Be forewarned that you probably won’t get your graded Prototype Report back before the Final
Report is due. (I have found that it makes more sense for me to grade them in parallel.) For this
phase of the project, all blocks for each design should be completely designed, laid out, and
simulated with SpectreS. The report should include:
- Header section
- Project overview: Give a one paragraph description of the function the project performs, whether you are doing two implementation or two architectural alternatives and what those alternative are, updated floorplans (with a plan for the VDD and GND wiring) with block interconnections and I/Os labeled, and updated clocking plans.
- Block design: For each block in each design:
- Description: Give a one-paragraph description of the function of the block.
- Block data: Give the following summary information about the block: name, list of inputs and outputs, size (L x W), peak power consumption, and the delay of the worst-case path.
- Block design: For each block give transistor-level diagrams and layout plots.
- Block verification: For each block give SpectreS command files (exclude the circuit net list) and output plots with an explanation of the simulation. Specify what percentage of the block input space was simulated (e.g., if you only simulated 4 data transition for a block with 2 inputs, you have only simulated 1/3 of the set of possible input transitions). Show and explain where the worst-case delay and the peak power was found for the input transitions you tried. The files must include explanation of the simulation (correct functioning and timing). Any simulation that is not well documented will not be graded.
- Comparison: Give a comparison (based on the work you have done so far) of the two approaches you are pursuing. If you are working on two different implementations of the same architecture, list the advantages and disadvantages of each approach. If you are working on two different architectures for the same function, give the advantages and disadvantages of each.
Project Final Report
This report accounts for 35% of the project grade.
Complete the project; for both designs all blocks should be interconnected in
Cadence and simulated as a single unit in SpectreS if possible (if your design
is too large to simulate from the layout, a VHDL/Verilog simulation will be acceptable).
All signal input/output from external to your design should be brought to the perimeter
of the design (and labeled); this includes VDD, GND, all clock signals, etc. All VDD, GND,
and clock signal wires must be interconnected.
Verify that each design functions correctly; one half of this report grade is based on
this (i.e., you must have a verified working design). The report should include:
- Header section
- Project overview: Give a one paragraph description of the function the project performs, whether you are doing two implementation or two architectural alternatives and what those alternative are, and final floorplans with block interconnections and I/Os labeled (e.g., an unexpanded Cadence layout identifying blocks and I/O). Describe your clocking schemes.
- Project data: Give the following summary information about each design: list of inputs and outputs, size (L x W), peak power consumption, and the delay of the worst-case path.
- Project simulation: For each design, give a SpectreS simulation of the critical path for timing verification (from the layout if possible). The file must include explanation of the simulation. Any simulation that is not well documented will not be graded. For projects where speed is a factor, determine the maximum operating speeds, or other relevant timing information.
- Optimizations:
- Layout area modifications: Describe any modifications to the designs that were done to optimize the area of the chip.
- Performance enhancements. Describe any modifications to the designs that were done to improve performance (speed and/or power consumption). Discuss delay and/or power consumption simulation results before and after changes.
- Conclusions: Compare your two designs - what are the strong and weak points of each, what alternate approaches might have resulted in further improvements, etc. Include alternatives that were considered but not actually implemented. If your design were fabricated, how would you test it?
Areas you need to think about
- How will I TEST my chip and show that it works - you should think about this while you are designing.
- How can the project decompose into parts and what is the best decomposition to save area, wire, and speed?
- How will I document the project to show my design, my simulation, and testing plans?
- Will there be some conclusions that I may reach in the project? Any report must have conclusions - yours should have one too.
- You must follow the class schedule! Time is a very important factor. Your success will depend on how good you are at using the time you have.
Additional Project Ideas
Here are some ideas to get you thinking about the types of designs that would be appropriate for your project.
- Data Compression Hardware
- 8-bit Microprocessor (using known instruction set - Intel, Motorola)
- FIR, IIR Filter
- DSP
- RSA Public Key Encryption
- High-speed Multiplier
- NTSC TV Scrambler/Descrambler
- FFT
- Floating Point Math
- CORDIC
- Neural Network
- Cache Controller
- DMA Controller
- Echo Canceller
- MPEG-3 Chip
Sample Projects |
|
