Cadence Labs

• Lab 1: Signing the MOSIS NDA
• Lab 1: Configuring your UNIX environment for Cadence - Complete STEPS #0-10
• Lab 1: Inverter Schematic + Symbol
• Lab 2: Inverter Simulation: Transient
• Lab 2: Inverter Simulation: DC w/parametric (VTC + sizing)
• Lab 3: Inverter Layout, DRC, Extraction, & LVS
• Lab 4 + 5: NAND gate Schematic + Test Bench + Simulation (DC + VTC) + Layout
• Lab 5: Cell Interconnection and Project Overview (discussed in lab)
• Lab 6: Back Annotation and simulation off extracted view + Quiz 1 (discussed in lab)
• Lab 7: Dynamic Circuits using Domino Logic
• Lab 8: Modeling of Routing Wires
• Lab 9a: Assignment
• Lab 9b: Inverter Simulation: Using Verilog as test stimulus (Mixed Signal)
• Lab 9c: NAND Simulation: Using Verilog as test stimulus (Mixed Signal)
• Lab 10a: Final Project Setup: Setting up a Group Project Library
• Lab 10b: Final Project Setup: Copying cells into Project Lib
• Lab 10c: Final Project Setup: Sharing Simulation States
• Lab 11: Final Project: Importing, Connecting, and simulating the PAD Frame