Cadence Labs
Lab 1: Signing the MOSIS NDA
Lab 1: Configuring your UNIX environment for Cadence - Complete STEPS #0-10
Lab 1: Inverter Schematic + Symbol
Lab 2: Inverter Simulation: Transient
Lab 2: Inverter Simulation: DC w/parametric (VTC + sizing)
Lab 3: Inverter Layout, DRC, Extraction, & LVS
Lab 4 + 5: NAND gate Schematic + Test Bench + Simulation (DC + VTC) + Layout
Lab 5: Cell Interconnection and Project Overview (discussed in lab)
Lab 6: Back Annotation and simulation off extracted view + Quiz 1 (discussed in lab)
Lab 7: Dynamic Circuits using Domino Logic
Lab 8: Modeling of Routing Wires
Lab 9a: Assignment
Lab 9b: Inverter Simulation: Using Verilog as test stimulus (Mixed Signal)
Lab 9c: NAND Simulation: Using Verilog as test stimulus (Mixed Signal)
Lab 10a: Final Project Setup: Setting up a Group Project Library
Lab 10b: Final Project Setup: Copying cells into Project Lib
Lab 10c: Final Project Setup: Sharing Simulation States
Lab 11: Final Project: Importing, Connecting, and simulating the PAD Frame
References Needed for Labs
Removing Cadence Lock Files
Importing Pad-Frame, simulating off extracted view
Exporting final project to GDS format
Exporting final project in CIF format - only for cadence 5.41, not 6.0
References Needed for HW
Homework Policy
Homework Sample Format (word)
Homework Sample Format (pdf)
Homework #1 Solution Q2
Sample Exams
Fall 08 Sample Midterm
Fall 07 Sample Midterm
Fall 04 Sample Midterm
Fall 04 Sample Midterm Solutions
Fall 04 Sample Final
Magic 7.1
Setting up Magic Tools
Magic Tutorials
MOSIS Documents
MOSIS Non Liaison Form (Individual Student Fills out and returns to GTA)
MOSIS Liaison Form (GTA fills out for whole class)
MOSIS Link to: ON/AMI .5 micron process description
MOSIS Link to: ON/AMI .5 micron process electrical (SPICE) parameters
MOSIS Link to: ON/AMI .5 micron process layer map
MOSIS Link to: ON/AMI .5 micron process design rules
Local Link to: ON/AMI .5 micron process design rules manual