| Week of: |
Lecture |
Lab |
Reading |
| 1/13/03 |
Introduction to the course; Overview of Testing; Defects, Failures, and Faults; Design Representation |
Introduction to the CAD Workstations and VLSI Tools. |
PTES: Ch1-3 |
| 1/27/03 |
VLSI Design Flow; Introduction to ASICs; Programmable ASICs |
|
PTES: Ch4
Smith: Ch1,4 |
| 2/3/03 |
Verilog HDL 1 |
|
Smith: Ch11 |
| 2/10/03 |
Verilog HDL 2 |
|
|
| 2/24/03 |
Logic Synthesis; Simulation;
PROJECT ASSIGNED |
|
Smith: Ch12,13 |
| 3/3/03 |
Role of Simulation in Testing; Automatic Test Pattern Generation; Current Testing. |
|
PTES: Ch5-7 |
| 3/10/03 |
Ad Hoc Test Techniques;
MID-TERM Review |
|
|
| 3/24/03 |
MID-TERM EXAM
Ad Hoc Test Techniques (cont). |
|
PTES: Ch8 |
| 3/31/03 |
Scan-Path Design |
|
PTES: Ch9 |
| 4/7/03 |
Boundary-Scan Testing |
|
PTES: Ch10 |
| 4/14/03 |
Built-in Self-Test |
|
PTES: Ch11 |
| 4/21/03 |
Memory Testing; Testing FPGAs and Microprocessors |
|
PTES: Ch12,13 |
| 4/28/03 |
Synthesis for Testability; Testing SOCs |
|
PTES: Ch14,15 |
| 4/30/03 |
Project Presentations |
|
|
| TBD |
FINAL EXAM (comprehensive) |
|
|
