Introduction

Design an 8 bit CISC processor. The general information, instruction set, timing, and block diagrams for the processor are given on the following pages. The 30 instructions are subdivided into 3 addressing modes and 2 branching modes. The addressing modes are: Inherent (INH), Immediate (IMM), and Direct (DIR). The branching modes are: Absolute (ABS) and Relative (REL). The processor's timing is based on a 4 phase cycle, with each instruction taking 1, 2, or 3 cycles to complete the execution of that instruction. Inherent instructions take 1 cycle, immediate instructions take 2 cycles, and direct instructions take 3 cycles. Build the processor from 4 sub-modules: ALU, PC, CU and IO. The ALU (Arithmetic Logic Unit) will perform the arithmetic. The PC (Program Counter) will keep track of where the CPU is within a program. The CU (Control Unit) will provide the decoding of the instructions and the proper timing of the other modules. The IO (Input/Output) module will handle interfacing with the exterior world.

Connect your CPU to the clock module and memory module. These modules will be provided to you. Four test stimulus modules will also be provided to aid in your development and testing of the CPU. The test modules will run assembly programs (also provided, hex files) loaded into the memory attached to your CPU. Test module #1 is a preliminary test and test one command from each section. Test module #2 runs through all the commands, (except branching commands,) and tests each command. Test module #3 extensively tests the branching commands. Test module #4 is a polynomial evaluator program.

For the design and testing of the processor, use the Verilog-XL simulator. Create your design using structural verilog.

At the end of the semester you will be required to demonstrate the functionality of your CPU to the Instructor and submit a report about the CPU. This report should include: a few pages describing your approach, all verilog code, simulation test modules, SignalScan printouts, and any other simulation results.

The project must be the result of the work of the group (at most 2 students) who will be credited with the grade.