Your objectives in this experiment are:

• To test a CMOS inverter using the 4007 MOS array chip

• To simulate a CMOS inverter using the IRF9140 and IRF150 MOS transistors in SPICE

• To design a CMOS NAND gate and a CMOS NOR gate both using 4007 MOS chip and using the IRF9140 and IRF150 MOS transistors in SPICE

• To compare propagation delays of these gates.

1. Simulate (PSPICE) the circuit above for the K parameter of the p transistor (Kp) being equal to K parameter of the n transistor (Kn) . Repeat the simulation for Kp = 4 Kn, Kp = 2 Kn, Kp = 0.5 Kn, and Kp = 0.25 Kn. Compare the output graphs and comment on each case.

 

2. Simulate the circuit above for the temperature values of 100K, 300K, and 500K, separately. Compare and comment on the output graphs.

c) Connect 100 nf load capacitor to the output of the circuit .Simulate this circuit for Kp = 4Kn , Kp= 2Kn, Kp= 0.5 Kn and Kp = 0.25 Kn and measure low-to-

high and high-to-low propagation delay of the inverter for each case.

d) Connect one more inverter to the output of the circuit above and measure low-to-

high and high-to-low propagation delay of the same inverter again. Compare the

values with those obtained in part (c ) and comment on the load capacitance of

the second inverter.

a) Completely assemble the circuit above using the 4007 MOS array chip. Pin numbers 9 , 10, 11, and 12 of the 4007 MOS array are indicated on the schematic above. Place one voltmeter between the output and the ground of the circuit to measure the output voltage. Keep VDD set to 5 VDC while you step V1 ( gate-to-source voltage) in 0.25 VDC increments starting at 0 and stopping at 5 Volts.

• Measure the output voltage for each increment of VGS (V1 here).
• Measure the drain current and find the input voltage value when drain current is maximum( let this voltage value be Vm).
• Measure the input voltage when it is equal to output voltage. Check whether this value is close ( or equal to) Vm measured in part b.
• Write a comment on the drain current vs input voltage characteristics.

• Design a NAND gate using the 4007 CMOS chip. Either 1) apply two different 5 Volt square -wave signals operating at the same frequency with different duty cycles or 2) apply 5 Volt DC source to one of the inputs and square-wave signal to the other input and then replace the input connections with each other to observe output vs. input characteristics.
• Make the same design in SPICE using IRF150 and IRF9140 transistors and plot the output vs. input voltage characteristics .
• In SPICE, connect a 100 nf capacitor to the output of the NAND gate, and measure low-to-high and high-to-low propagation time delays of the NAND gate. Repeat the same experiment for 100pf, 1 m f, and 10 m f capacitors. What kind of relation can you observe between load capacitance and propagation delay of the gate.

• Design a NOR gate using the 4007 CMOS chip. Either 1) apply two different 5 Volt square -wave signals operating at the same frequency with different duty cycles or 2) apply 5 Volt DC source to one of the inputs and square-wave signal to the other input and then replace the input connections with each other to observe output vs. input characteristics.
• Make the same design in SPICE using IRF150 and IRF9140 transistors and plot the output vs. input voltage characteristics .
• In SPICE, connect a 100 nf capacitor to the output of the NOR gate, and measure low-to-high and high-to-low propagation time delays of the NOR gate. Repeat the same experiment for 100pf, 1 m f, and 10 m f capacitors. What kind of relation can you observe between load capacitance and propagation delay of the gate.

Compare the propagation delays of NAND , NOR and Inverter gates when load

capacitor is 100nf. Which one is the fastest? Why? ( Bonus will be given to those who can explain the reason mathematically)