CS 211- Homework 2: Due September 30, 6pm.

Submit using Blackboard only.

1. Several researchers have suggested that adding a register-memory addressing mode to a load-store machine might be useful. The idea is to replace sequences of

LOAD R1, 0(Rb)

ADD R2, R1, R2

by the single instruction

ADD R2, 0(Rb)

Assume that the new instruction will cause the clock cycle of the processor to increase by 5%. Use the instruction frequencies for the gcc benchmark on the load-store machine from Figure B.27 in the textbook. The new instruction affects only the clock cycle and not the CPI.

(a) What percentage of loads must be eliminated for the machine with the new instruction to have at least the same performance ?

(b) Can this be applied for all sequences of load followed by operation, or is there a situation where this cannot be used?

2. Consider the following segment of code, and assume you have to schedule it on a MIPS type pipeline.

load R0, (R4)

add  R1, R0, #10

load R2, (R5)

mul  R0, R2, #10

mul  R4, R2, R1

store R0, (R5)

Assume you have a standard MIPS type pipelined processor with 5 stages (Fetch, Decode, Execute, Memory, Write-back). Answer the following questions, and explain all your answers.

• (a) What are all the data dependencies, and the type of dependency,  in the above code ?
• (b) If you have no forwarding, do you have stalls in the above code ?
• (c) Next, if the pipeline had internal forwarding – are there any stalls left in the code ?
• (d) Finally, can the above code be rearranged to further minimize the stall cycles ? .