Research Projects
- Research Interests: Embedded
Systems,
Software security, Optimizing Compilers, Pervasive
Computing, Computer Architecture, Networks and
Distributed
Computing, Electronic Commerce
- Brief
CV
(pdf)
Ongoing Research Projects
Hardware/Software Approaches to Software
Security
The new-found ubiquity of embedded processors in consumer and
industrial applications brings with it an intensified focus on
security, as a strong level of trust in the system software is crucial
to their widespread deployment. The growing area of software protection
attempts to address the key steps used by hackers in attacking a
software system. In this research, we explore software protection
approach that utilizes a hardware/software codesign methodology.
The
specific focus of our research is exploring the role of hardware in
creating more secure embedded systems and specifically the question of
how hardware
can assist us in providing secure platforms. One of our objectives is
to consider attacks on secure applications, such as military
applications, where software execution
takes place in an entirely encrypted form. While it is thought that
encrypted
execution effectively
deters
any kind of attack, we in fact show that several types of attacks of still
possible. Our research explores an integrated
hardware-software
co-design approaches that aim to combine novel techniques in the
areas of compilers, architecture and software security in order to provide a
high level of both security and adaptability by. By utilizing a secure
hardware coprocessor in the form of a reconfgurable logic (such as a
Field-Programmable
Gate Array - FPGA), we aim to provide solutions that do not require
re-design of the processor instruction set and can be implemented using
COTS technology. The secure hardware component
accelerates
execution of programs in a secure environment, while the reprogrammable
nature of FPGAs provides us with the flexibility to carry out
application specific
compiler-driven protections and therefore the ability to adapt the
security mechanism to the needs of the application.This research
is supported by grants from National Science Foundation
(NSF-ITR program) and Air Force Office of Scientific Research (AFOSR).
Relevant Recent
Publications
-
“A
complier-hardware approach to
software protection for embedded systems”, Olga Gelbart, Eugen Leontie,
Bhagi Narahari, Rahul Simha, (accepted to appear in) International
Journal of Computers and Electrical Engineering. Special issue on
Real-time and
Multimedia security.
-
“Compiler
directed region-based
security for low overhead software protection”, Vijay Kongubangaram,
Olga
Gelbart, Rahul Simha, Bhagi Narahari, 3rd IEEE
International
Symposium on Dependable, Autonomic and Secure Computing (IEEE-DASC 2007),
Sept., 2007.
- "Integrated Hardware-software approaches
to software security", B. Narahari and R. Simha, Cyber Defense
Conference, Information Assurance Science and Technology Series,
Griffis Institute, Rome Air Force Labs, Rome, NY, May 2007.
<>- “Compiler-FPGA Technique to Detect
Memory
Spoofing in Encrypted-Execution
Platforms”, E. Leontie, O. Gelbart, B.
Narahari, R. Simha, 6th Annual Security Conference,
April 2007
-
“Privacy-preserving
programming using Sython”, M. Gaiman, R. Simha, B. Narahari, Computers
and
Security, No. 26, 2007.
- "Secure
execution with components from Untrusted Foundries”, (with R. Simha, J.
Zambreno, A. Choudhary), to appear in Advanced Networking and
Communications
Hardware Workshop (ANCHOR), held in conjunction with Int. Symposium
on
Computer Architecture (ISCA 2006), June 2006.
- "High performance software protection using reconfigurable
architectures”, (with J.Zambreno, D.
Honbo, A. Choudhary, R.
Simha), Proceedings of the IEEE Journal, Vol.94, No.2, Feb.
2006.
- "SPEE: A secure program execution environment using code
integrity checking", (with O. Gelbart, R. Simha), Journal of
High Speed Networks
, Volume 15, Number 1, 2006 pp. 21-32.
- "SAFEOPS: An approach to embedded software security", ACM Trans.
Embedded Systems, Feb. 2005, (with J. Zambreno, A. Choudhary, R. Simha,
N. Memon).
- "Performance study of a Compiler/Hardware approach to
Embedded Systems security", IEEE-Internationl Conference on
Intelligence and Security, 2005, (with K. Mohan, P. Ott, R. Simha, J.
Zambreno, A. Choudhary).
- "CODESSEAL: A Compiler/FPGA Approach to Code Security",
IEEE International Conference on Intelligence and Security, May 2005,
(with O. Gelbart, P. Ott, R. Simha, J. Zambreno, A. Choudhary).
- "SPEE: Secure Program execution environment tool using static and
dynamic code verification ", 3rd Trusted Internet Workshop, held in
conjunction with HIPC 2004, (with Olga Gelbart, R. Simha).
- "An overview of Security-driven Compilation", Workshop on
New Horizons on Compiler analysis and optimization, held in
conjunction with IEEE-HIPC 2004, Dec. 2004 (with R. Simha, A.
Choudhary, J. Zambreno).
- "Flexible software protection using Hardware/Software codesign
techniques", Proc. Design, Automation and Test Europe (DATE '04) (with
J. Zambreno, A. Choudhary, R. Simha).
Compiler
Optimization for ILP Architectures
Recent architectures, such as Intel's IA-64 family, are based on the
EPIC (Explicitly Parallel Instruction Computing) architecture. EPIC
processors
provide a large degree of hardware parallelism, but as opposed to
superscalar
processors, require that dependence analysis and scheduling be done
entirely
by the software -- thus making the role of the compiler even more
critical.
they require that parallelism be extracted by the compiler.Our projects
have focused on developing an Optimizing Assembler for EPIC
Architectures,
and developing a research compiler infrastructure for Intel's IA-64
processor. Funded in part by National Security Agency, under the LUCITE
program.
- SPASM: An Optimizing Assembler for EPIC/VLIW Architectures:
Numerous
statements
have been made concerning the feasibility of programming multi-unit
processors
at the assembly language level. This research, however, focuses on
the
development of techniques to support the development of an optimized
EPIC
assembler. This research explores methods to perform block formation,
register
allocation, instruction scheduling, and code generation using assembly
language source code as input. These topics form the foundation for the
development of optimizing assemblers for EPIC processors.
- TRITANIUM: This project developed a backend IA-64 code
generation
module
for the Trimaran Compiler Infrastructure -- called Tritanium.
This
infrastructure allows researchers to develop front end and backend
compiler
optimization techniques and test their effectiveness on Intel's Itanium
processor. Source code is downloadable at the
Tritanium Website.
Relevant Recent Publications:
- "Tritanium: Augmenting the Trimaran Compiler Infrastructure to
support
IA-64 Code Generation", EPIC-1 Workshop (held in Conjunction with
Micro-2001),
2001, Y.L. Chobe, B. Narahari, R. Simha, W. Wong; download
pdf
- "SPASM: Parallelizing Assembler for EPIC/VLIW Processors", B.
Narhari,
R. Simha, A.Jayaraj, Y. Williams, Y. Chobe. pdf
file
- "Fine Grained Register Allocation for EPIC Processors with
Predication",
Hansoo Kim, Kanchi Gopinath, Vinod Kathail, Bhagirath Narahari, The
1999 International Conference on Parallel and Distributed Processing
Techniques
and Applications(PDPTA '99), Las Vegas, Nevada, USA. June 28 - July 1,
1999.
Embedded Systems
- Power-aware compiler toolset (funded by NASA and
Intelligent Automation Inc.) Goals: Design and
build a
compiler to optimize power consumption; investigate algorithms for
resource
allocation. The focus of our research is in the development of compiler
optimization techniques for embedded applications . Specifically, the
research
is investigating compiler techniques to minimize the power consumed by
memory devices on an embedded system.
- Rapid Prototyping Infrastructure for Embedded Networks (funded by
National Security Agency). The
research
goal
is to examine issues in developing platforms for future embedded
networks.
In particular, for larger nodes, a Java-based platform will provide the
advantages shared by Java development platforms for the desktop.
However,
such an approach requires careful examination of resource usage and
should
present the developer with the opportunity to exploit hardware.
Furthermore,
instead of re-writing a JVM for each new hardware, there is a need for
modularly constructing JVM’s to allow for software development to keep
pace with new hardware. This project examines the development of a
configurable
JVM for embedded systems.
Relevant Recent Publications:
- ``Memory Issues in Power-Aware Design of Embedded Systems: An
Overview'',
CASES 99 (Workshop on Compiler and Architecture Support for Embedded
Systems),
Washington DC, August 1999 (with R.Levy, B.Crilly and R. Simha).
- "Application Specific Memory Partitioning for Low Power",
Proceedings
of
ACM COLP 2002 (Compiler and Operating Systems for Low Power), September
2002, (with S. Udayakumaran, R. Simha). pdf
file
- "Assembly Code Level Power Optimization for Partitioned Memory
Architectures", ACST 2004, (with R. Levy, R. Simha).
- "Energy-aware Allocation fo Dynamic Variables in Partitioned
Memory Architectures", Workshop on New Horizons on Compiler analysis
and optimization, held in conjunction with IEEE-HIPC 2004, Dec. 2004
(with R. Levy, R. Simha).
Selected Recent Publications in Other Areas
- "Simulated Chemotaxis: A biologically inspired framework for a
class of wireless coverage problems", O. Sanli, R. Simha, B. Narahari, Int. Journal of Adhoc and Sensor Wireless
Networks, Vol.2, No.4, 2006.
- "Strong minimum energy topology: NP-completeness and
Heuristics", X. Cheng, R. Simha, X. Cheng, B. Narahari, D. Liu, IEEE Trans. Mobile Computing, Vol.2,
No.3, 2003.
- “Energy
Balance in Wireless Sensor Networks Using Connection Segmentation and
Range
Control”, N.K.Singh, B.Narahari and R.Simha, in Proceedings of IEEE WACE 2003.
- ``Dynamic
Load Balancing Schemes for Computing Accessible Surface
Areas
of Protein Molecules'', E. Suh, B. Narahari, R. Simha, IEEE
Int. Conf. High Performance
Computing (HIPC 1998), 1998.
- ``A real-time parallel scheduler for the imprecise computations
model'',H.
Foaud, B. Narahari and J. Hahn, Journal of Parallel and Distributed
Computing Practices, Vol.2, No.1, 2000
- ``Routing and Scheduling I/O Transfers on a Wormhole-Routed
Mesh'', B. Narahari, R. Simha, S. Shende, S. Subramanya, Journal
of Parallel and Distributed Computing, Vol. 57, No. 1, April 1999.
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